The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing Gate Induced Drain Leakage (GIDL) current by selectively increasing electrical gate oxide thickness only in the gate/drain overlap region during the fabrication of integrated circuits.
In the fabrication of integrated circuits, as the sizes of semiconductor devices, such as state-of-the-art Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are scaled down, performance issues regarding the current driving capabilities of these devices exist. Since the current driving capability is a function of both source resistance and gate oxide thickness, better performance in these devices is achievable through thinner gate oxide and spacer layers. However, it has been observed that as the gate oxide is made thinner, gate-induced drain leakage (GIDL) currents degrade the performance of these devices as the GIDL currents become a larger percentage of the total sub-threshold leakage current. The GIDL currents are due to electrons from the valence band tunneling to the conduction band as a result of excessive band bending in the gate/drain overlap region. As these semiconductor devices scale down, the layer thickness of the gate oxide must continue to be reduced in order to provide for suitable gate control over the sub-threshold region. Also, doping density in the channel and source/drain regions must increase to improve punch through characteristics and increase drives. Unfortunately, it has been observed that by increasing the doping density in the channel and source/drain regions, the surface electric field also increases, resulting in more band bending and hence, even more GIDL current. Thus, difficulties exist in providing a scaled down semiconductor device having a suitable balance between high current driving capability and low GIDL current.
One approach for reducing GIDL currents involves symmetrical oxidation in order to provide a thick gate oxide only in the regions of the gate-source and gate-drain overlap. The thick gate oxide in the gate-drain region reduces GIDL. However, having a thick gate oxide in the gate-source region increases source resistance, which in turn, reduces the current driving capability of the device.
Another approach is disclosed by U.S. Pat. No. 5,684,317 to Hwang, who teaches forming a thick oxide layer only in the gate-drain region in order to reduce GIDL current without increasing source resistance. The material thickness of the oxide layer in the gate-drain region is increased by implanting an oxidation accelerating material, such as chlorine or fluorine, to physically grow a thicker gate oxide layer in that region. Due to the presence of the oxidation accelerating material, the oxide layer in the gate-drain region grows faster than the remaining portions on the substrate. However, having an increased material thickness of the oxide layer in the gate-drain region hampers current drives of the transistor and also cause increased stress in the active area near the overlap region due to volume expansion.
Accordingly, a need exists for a scaled-down semiconductor device having a thinner gate oxide with improved electrical performance which overcomes the disadvantages of the prior art. The semiconductor device and its method of fabrication should be cost effective and manufacturable, should be easily integrated into an existing process flow, and should not significantly increase the cycle time of the process flow.
The present invention provides a method by which field effect transistor (FET) devices are produced having lower gate induced drain leakage (GIDLs) than FET devices with a similarly thick gate oxide layer formed by conventionally known methods. The method of the present invention, as explained hereafter, may be used in the fabrication of all N-channel, P-channel, and CMOS FET devices.
The method of the present invention employs a non-orthogonal ion implant process by which the gate-oxide layer in the gate-drain overlap region of a FET device is selectively doped with fluorine or chlorine ions. The dosage of the ion implant is such that the ion concentration increases the xe2x80x98electricalxe2x80x99 gate oxide thickness near the gate-source/drain corners, thereby lowering the dielectric constant of the gate-oxide layer in the gate-drain overlap region without actual thickness growth to the ion doped gate-oxide layer. Since GIDL is exponentially dependent on the magnitude of the surface electrical field, even a slight reduction in the electrical field results in a dramatic reduction in GIDL. Accordingly, supplementing existing FET fabrication processes with the method of the preset invention, lowers the effective surface electrical field in the overlap region, and thereby minimizes GIDL in FET devices wherein the present invention is practiced.
The method of the present invention may be employed in any FET device which is susceptible to increased GIDLs due to a xe2x80x98thinxe2x80x99 gate oxide layer. The method of the present invention may be practiced upon N-MOSFET devices within integrated circuits including but not limited to Dynamic Random Access Memory (DRAM) integrated circuits, Static Random Access Memory (SRAM) integrated circuits, Erasable Programmable Read-Only Memory (EPROM), and Application Specific Integrated Circuits (ASICs). Also, the method of the present invention has broad applicability and may be practiced upon P-MOSFET and CMOS devices within integrated circuits, as the process is applicable to the fabrication of those devices.
In accordance with one aspect of the present invention, provided is a circuit structure comprising a semiconductor layer; an oxide layer formed on the semiconductor layer; a polysilicon layer formed on the oxide layer; a gate structure formed from the polysilicon layer, the gate structure having a defined leading edge; and an overlap region beneath the gate structure and adjacent the leading edge having a predetermined ion implant concentration, the predetermined implant concentration is sufficient to increase the electrical gate oxide thickness in the overlap region.
In accordance with another aspect of the present invention, provided is a method for fabricating a structure on a semiconductor layer comprising the steps of forming an oxide layer on a semiconductor layer; forming a polysilicon layer on the oxide layer; patterning the polysilicon layer into a gate structure having a defined leading edge, and to expose the oxide layer; and implanting ions into the oxide layer at an overlap region beneath the gate structure and adjacent the defined leading edge to a predetermined ion implant concentration which is sufficient to increase the electrical gate oxide thickness only in the overlap region without thickness growth of the oxide layer, the ions being implanted at a tilt angle non-orthogonal to the plane of the semiconductor layer.
In accordance with still another aspect of the present invention, provided is a method of reducing Gate Induced Drain Leakage (GIDL) current within Field Effect Transistors (FETs) comprising the steps of: forming on a semiconductor substrate a field effect transistor structure comprising a gate oxide layer, a gate electrode on the gate oxide layer and two source/drain regions formed within the semiconductor substrate; annealing the semiconductor substrate; implanting ions into the gate oxide layer beneath the gate electrode and adjacent the drain region, which defines an overlap region, to a predetermined ion implant concentration which is sufficient to increase electrical gate oxide thickness only in the overlap region, the ions being implanted at a tilt angle non-orthogonal to the plane of the semiconductor substrate; and completing the fabrication of the semiconductor substrate.
An object of the present invention is to provide a method of reducing gate induced drain leakage current by selectively increasing the electrical gate oxide thickness only in the gate/drain overlap region during the fabrication of integrated circuits.
Another object of the invention is to provide a manufacturable method for fabricating integrated circuits which will result in reduced gate induced drain leakage.
Other objects, features and advantages will appear more fully in the course of the following discussion.